By Louis Fan Fei, Garmin International
The three major building blocks in a modern, fully-integrated transceiver are a transmitter (TX), a receiver (RX), and a synthesizer. A synthesizer design is quite different from the TX or the RX. Both a TX and a RX have a higher analog content. The synthesizer design has significantly higher digital content. It challenges the designer’s analog and digital skills.
In some instances, what appears to be an analog function is actually implemented with a digital block. For example, a frequency divider and a phase/frequency detector (PFD) are routinely implemented with the digital building blocks. In other instances, what appears to be a digital block needs a carefully analog design, such as a charge pump (CP). In the voltage controlled oscillator (VCO) design, both analog and digital building circuits are needed. The required knowledge of mixed-signal circuits makes a synthesizer a challenging design to work on.
A synthesizer is used to generate a very stable carrier signal for the TX and the RX. It is used to switch a transceiver to a different channel. The important requirements are: integrated in-band phase noise, spur level, channel switching speed, frequency step resolution, local oscillator pulling, power consumption, and low power supply rail.
The two popular synthesizer architectures are an integer-N and a fractional-N phase-locked loop (PLL). If an integer-N PLL can meet the requirement, it should be used because of a relatively simpler design. But in most cases, especially the multi-band, multi-mode transceivers used in cellular applications, a fine frequency resolution and a fast switching time are needed. In those cases, a fraction-N will have to be used. There are many good references on the synthesizer system and the digital control block design. This paper focuses on the detailed analog/RF circuit portion. The CP, PFDs, frequency dividers, VCOs are discussed below. All the pure digital signal processing (DSP), such as delta-sigma (Δ Σ), are left out because it is a topic all by itself.
1. CMOS charge pump
Charge Pump
A charge pump (CP) is used in the synthesizer to source or sink current from an external loop filter. The basic idea is to add a switch in both the current source and current sink paths. The switch can be added at the gate, source, or drain. To reduce the effect of the charge sharing, clock feed-through, and charge injection, switching at the source is the best choice because the switch is relatively isolated from the output. Switch at source topology is shown in Figure 1a. Icp is the reference current for both the current sink and the current source. For the current sink path, Icp is mirrored into the M6&M5 path through the modified stacked current mirror (M1, M2, M5, M6). The advantage of this current mirror is the low supply voltage requirement compared with the standard stacked current mirror. M15 is the source switch for the current sink. M13 is the dummy FET to ensure M1 and M5 have the same DC source voltage. For the current source path, Icp is first mirrored by modified stacked current mirror (M1, M2, M3 and M4). Then it is mirrored again by the PMOS current mirror (M7, M8, M9, M10). M11 is the switch for the current source.
To reduce the mismatch problem and to increase the speed of the CP, a current steering CP (Figure 1b) is often used. The switches are implemented with a current steering pair (M1&M2, M3&M4). Icp is mirrored to the current steering pair via the modified stacked current mirror. To source the current, UP is logic H and /UP is logic low. Icp goes through the path of M1, then it reaches output via another current mirror (M5&M6). To sink the current, DOWN control pair is activated. Because the current is steered instead of charging/discharging, Figure 1b will be faster than Figure 1a. But it will burn more power since the current path is not really shut off when it is not used.
Phase/Frequency Detector
The UP/DOWN control signals used in the CP are generated by the phase/frequency detector (PFD). The two D-type flip-flop (DFF) implementation has been a work horse for a long time. Its block diagram and the circuit implementation are shown in Figure 2a. The upper and lower DFFs generate UP and DOWN signals, respectively. When f1 arrives first at the upper DFF, the UP signal is generated to turn on the current source. When f2 arrives at the lower DFF, its output is logic H. When both UP and DOWN are logic H, NAND gate resets both DFFs to output logic L. Thus the phase difference between the two signals are detected and used to turn on either the current sink or current source of the CP.
2a. CMOS PFD
To improve the speed, simplicity is key. By using the faster and simpler logic, like the true single phase clock (TSPC), the DFF can be implemented with just a few transistors instead of a few gates. One popular implementation is shown in Figure 2b. Transistors from M1 to M9 forms the upper latch, while the transistors from M11 to M19 form the bottom latch. The two latches are identical.
2b. PFD with TSPC logic
On the upper latch, the FETs from M1 to M6 are basically a modified version of the standard doubled n-C2MOS latch with precharge technique. The theory of operation is as follows. Assume f1 and f2 are both low at the start. Node A is precharged to logic high. As f1 transition from low to high and f2 stays low, M5 is turned on and M5 turns on the inverter formed by M4 and M6. Node B is pulled low. M7 and M8 is an inverter to give the UP signal. M9 is added to fix one special problem in this architecture. Because the top and bottom latches can’t be perfectly matched in delay, there will be narrow pulse for both UP and DOWN output even with no input phase difference. With M9, node A is discharged to GND. As f1 rises from low to high, node B is pulled up to logic H. Thus UP output will be pulled down. The bottom latch works on the same theory.
The reset circuitry is essentially built into this architecture. There is no feedback reset logic circuitry needed in the traditional PFD in Figure 2a. Because of this, the reset delay is short. The PFD with TSPC implementation will have a much higher operating frequency. (Low GHz operating frequencies have been reported by many researchers.)
Frequency Divider
Typically a divide-by-2 block is designed first. Then, multiple basic blocks are cascaded together to get a higher divider ratio. For the high-speed portion of the synthesizer, such as the prescaler that immediately follows the VCO output, source couple logic (SCL) is a good choice. The block diagram and the circuit implementation are illustrated in figure 3a.
3a. Frequency divider with ECL
As shown in the block diagram, the basic building block is the DFF (D type flip-flop). The two DFFs work in a master-slave fashion. In the first half of the clock cycle, the master DFF is on and the input data is clocked in. The slave DFF is off. In the second half of the clock cycle, the master DFF’s output is transferred to the slave DFF. The output toggles at the next clock edge. Thus, the output frequency will be half of the input frequency. A frequency divider is essentially a digital building block.
The circuit implementation is also shown in figure 3a. M1 to M8 form the master DFF. M9 to M16 are the second DFF. Since the two DFFs are identical, we can focus on just one DFF. M1 and M2 are the buffer for the input RF signal. M5 and M6 are the latch element. M2 and M3 are the logic element. M7 and M8 are the diode tied load. When RF input is high, M4 to M6 are shut off. The input at the M2&M3 pair is loaded into the DFF. When RF input is low, the already loaded inputs are latched into the M5&M6 pair. Because of the current steering technique used, the ECL is very fast. Thus, it is suitable for RF applications.
As the VCO output frequency is divided down, the operating frequency gets much lower after the prescaler. A simple and cheaper TSPC frequency divider can be used. The most basic form is shown in 3b.
3b. TSPC Frequency Divider
Transistors Q1 to Q6 form the master latches. Transistors Q7 to Q12 form the slave latches. Q13 and Q14 are simply the inverter to complete the feedback path needed in the toggle latch. The master latch is sometimes called double NC2MOS because two NFETs are needed in the pull-down network (PDN). Similarly, the slave latch is sometimes refereed as the double PC2MOS because two PFETs are needed in the pull-up network (PUN). When the clock is high, the master latch is activated while the slave latch is off. (The opposite is true when the clock is low.)
VCO
The CMOS VCO is based on the negative resistance theory. The NMOS-only version is presented in Fig 4a. By cross coupling M1 and M2, a positive feedback is created in the circuit. Looking into the gate of M1 and M2, a negative resistance can be expected. The operating frequency is set by the resonant tank. L1 and L2 provide the inductance part. The frequency can be tuned coarsely by the capacitance banks and fine tuned with the varactor caps. In Fig 4a, two bit 4 states capacitance banks are used. More banks can be added if a larger process variation is expected. By turning on/off M7 and M8, more/less total capacitance can be expected in the resonator tank. The varactor is implemented with FETs M5 and M6 by tying the source and the drain. M3 and M4 are the output buffers.
4a. NMOS only VCO
Complementary CMOS VCO is presented in figure 4b. The key change is to add a cross coupled PMOS pair. By adding a PMOS pair, two more active elements are added to contribute the negative resistance while the bias current remains the same. So it is more power efficient.
4b. Complementary CMOS VCO
Since the DSP portion of the synthesizer is already in standard cell form, the development time for a fully integrated CMOS synthesizer can be greatly reduced. The circuit topologies presented here are generic and they are widely used. They can be considered as a good starting point for your next design.
References
1. Behzad Razavi, "RF Microelectronics," Prentice-Hall, 1998.
2. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, "VLSI design techniques for analog and digital circuits", McGraw-Hill, 1990.
3. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2001.
4. Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits", Cambridge University Press, 2004.
5. M. H. Perrott, High speed communication circuit and systems, MIT OCW 2003.
6. Allen Podell, RFIC Design and Applications, Besser Associates short course.
7. James Young, RF CMOS Design, Besser Associates short course.
8. Ulrich L. Rohde, David P. Newkirk, "RF/Microwave Circuit Design for Wireless Applications", John Wiley & Sons, Inc., 2000.
9. Jan Crols, Michiel Steyaert, "CMOS Wireless Transceiver Design," Kluwer Academic Publishers, 2003.
10. Louis Fan Fei, "CMOS Oscillator Design Considerations," Microwave Journal, April, 2007.
11. Louis Fan Fei, "Enhance CMOS Charge pumps and phase-frequency detectors," Microwaves and RF, Sep. 2007.
12. Louis Fan Fei, "Frequency divider design strategies," RF Design, March, 2005.
About the Author
Louis Fan Fei is currently an RF engineer at Garmin International where he has designed GPS receivers since 2003. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He also worked on microwave instrument circuits for HP/Agilent in Colorado Springs in the summer of 1997. He has more than 17 technical publications. He received his BEE and MSEE from Georgia Tech in 1996 and 1998, respectively.
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