Wireless communications are evolving at an ever-increasing rate. Systems suchas GSM, EDGE and CDMA are being augmented with 3G and Wi-Fi capabilities,making an efficient and cost-effective multimode solution essential. The RF transceiver is a key ingredient of any multimode solution. Its design presents several challenges that are magnified when distinctly different modes such as GSM and WCDMA must both be hosted. This article examines some of the challenges related to multimode transceiver design, and presents a highly integrated, multimode RF transceiver solution that addresses the needs of GSM, EDGE and WCDMA.
Wireless standards necessarily pursue a dual path of consolidation
and expansion, as if this were a law of nature. Market
forces demand this. Wi-Fi solution providers were quick to integrate
802.11a/g with their 802.11b solutions. GSM solutions necessarily
integrated EDGE. In the same manner, combined GSM-EDGEWCDMA
solutions are also unavoidable.
These same market forces drive the multimode aspect of transceiver
design as well as the multiband perspective. Solutions that were
acceptable for single- or dual-band applications may not be acceptable
for triple- and quad-band service where external component cost and
size become unacceptable. Transceiver designers must be increasingly
forward-looking in anticipation of these factors, while at the same time
employ measured restraint so that present customer demands are well
served in the near-term. The discussion that follows focuses on attaining
some of the more demanding requirements that are commensurate with
a highly integrated GSM-EDGE-WCDMA transceiver solution, and the
role these requirements play in transceiver architecture selection.
Industry-favored solutions for GSM-EDGE have converged to
primarily one of two choices for the receive architecture: a) directconversion
or b) low-IF. Aside from complexity and low-cost features
that these architectures provide, several technical issues have warranted
GSM-EDGE requires IP2 performance on the order of 50 dBm or
more when referred to the antenna input. This requirement amplifies
the already challenging issues pertaining to dc offsets in the receiver.
Direct-conversion receivers struggle with this problem more than
low-IF receivers since the dc component falls directly within the
receive bandwidth. The dc offset is also time varying because it is
driven by dynamic adjacent-channel interferers. It also is affected
by local oscillator (LO) leakage, low-noise amplifier (LNA) gain, and
CMOS designs must also contend with fairly severe 1/f noise in
the sensitive IQ gain stages that immediately follow the downconversion
mixer. Detailed 1/f noise parameters depend significantly
on oxide thickness and channel length. RF CMOS technologies
in the 130 nm to 180 nm realm generally exhibit 1/f corner
frequencies on the order of several hundred kHz, thereby making the
low-IF architecture attractive for this reason. Issues of dc offset
are not eliminated entirely with the low-IF architecture, but the
severity is reduced.
Most WCDMA receivers have adopted
the zero-IF architecture.Owing to WCDMA’s
much wider modulationbandwidth, dc
offset issues are moreeasily addressed than
for GSM-EDGE. The bandwidth argument
also reduces the 1/fnoise issue because
(i) its impact on the overall receive signalto-
noise ratio (SNR) is considerably less,
and (ii) this noise is spread across multiple chips of the WCDMA waveform where it can be
effectively tracked out by the baseband signal processing if desired.
One of the major problems facing WCDMA receiver design pertains
to transmitter leakage that falls through the duplexer filtering into the LNA input.
This leakage adversely impacts attaining receiver
IP2 and IP3 requirements, and normally requires band-specific SAW
filters to be used between the LNA outputs and the mixer input.
In WCDMA low-band, the transmit signal is offset from the receive
signal by a scant 45 MHz whereas the offset is increased to 190
MHz for the IMT band near 2 GHz. These offsets combined with the
required filter attenuation that is needed make the on-chip filtering
option quite challenging. Since the filter follows immediately after
the LNA, its insertion loss must be reasonable or else additional
constraints are imposed on the LNA gain. As shown in Figure 1, the ratio
of inductor-Q to filter-Q must be at least a factor of four in order to
have a reasonably small insertion loss.
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